The present invention relates to a technique especially effective for application to a nonvolatile memory having an internal booster, from which stored information can be electrically erased. For example, the invention relates to a technique effective for use in a flash memory employed for a portable electronic device.
In a portable electronic device, a volatile memory such as a DRAM and a nonvolatile memory such as a flash memory are used as memory devices of data. On the other hand, in a portable electronic device, a battery is used as a power source, and there is always a danger of occurrence of a dead battery. Due to this, in the portable electronic devices, a nonvolatile memory of which data is not erased even if the battery runs down is becoming the mainstream.
A flash memory uses, as a memory cell, a nonvolatile memory element comprising a MOSFET of a double gate structure having a control gate and a floating gate. By changing a fixed charged amount of the floating gate, a threshold voltage of the MOSFET is changed, thereby enabling information to be stored. Such a flash memory needs a high voltage (such as xc2x110V or higher) for changing the threshold voltage by pulling/injecting charges from/to the floating gate of the nonvolatile memory element in an operation of writing/erasing data to/from a memory cell. In the flash memory, the high voltage is generally generated by an internal booster provided in a memory chip.
In an operation of writing/erasing data to/from a memory cell in a flash memory having an internal booster, the internal booster is activated to boost an internal source voltage simultaneously with the start of the writing/erasing operation. After the internal source voltage is boosted to a predetermined voltage, a write voltage or an erase voltage is actually applied to a memory cell. Methods of determining a timing of starting an actual writing/erasing operation after the internal source voltage is boosted to a predetermined voltage include a method of determining the timing by monitoring a generated voltage and a method of determining the timing after elapse of a predetermined time on assumption that the internal source voltage has increased to the predetermined potential. In the former method, when the internal source voltage does not reach the predetermined potential for some reason, there is a fear that the program cannot escape from the writing or erasing operation. Conventionally, the latter method of determining the timing on the basis of time is generally employed.
In the method of determining the timing of actually applying the write voltage or erase voltage to the memory cell on the basis of time, however, the time required to boost the internal source voltage depends on the magnitude of an external source voltage, capability of the booster, and the load capacity of word line, bit line, or the like. The capability of the booster and the load capacity can be calculated from a designed circuit, and the external power source is determined in the specification. The timing is determined by calculating an expected time in which the internal source voltage is sufficiently boosted also in the case of performing the writing/erasing operation on a worst capacitor in the circuit in a state where a source voltage of the lower limit value determined in the specification (generally, a voltage lower than a source voltage used by about 10%) is applied.
In recent years, however, the variety of the external power source of the memory is increasing. For example, external power sources operating at 3.3V, 2.5V, 1.8V and the like are in demand. In a system using a memory, which is constructed on a substrate of a stay-at-home apparatus such as a personal computer, the source voltage is fixed. Consequently, there is no problem to determine the timing by calculating a time in which the internal source voltage is expected to be boosted by a booster with the source voltage (Vcc-10%) of the lower limit value determined by the specification. On the other hand, the memory used in the portable electronic device may operate on a DC voltage such as 3.3V converted from AC 100V, on a built-in battery of, for example, 1.8V, or the like.
In this case, even if 1.8V is supplied, when the timing is determined by calculating the time in which the internal source voltage is expected to be sufficiently boosted also in the case of performing the writing/erasing operation on the worst capacity in the circuit, the data writing/erasing operation can be performed with accuracy without a problem. In the case where the internal booster is constructed by using an MOSFET, however, when the operation voltage is 1.8V, the drain current of the MOSFET is about xc2xc of that when the voltage is 3.3V. Consequently, the time required to boost the internal source voltage increases by four times. For example, the data writing operation is finished in 1 mS (millisecond) when the source voltage is 3.3V. It takes, however, 4 mS when the source voltage is 1.8V. In an actual product, the writing/erasing timing is determined on the basis of 1.8V with which the writing operation takes longer time even in the case where the external source voltage is 3.3V in consideration of the possibility where the product is used with the external source voltage of 1.8V. Consequently, a problem such that the time required for the writing/erasing operation when the external source voltage is 3.3V is long more than necessary occurs.
Further, the inventors of the present invention have found that the time required to boost the internal source voltage varies also according to a pattern of write data. Specifically, in association with an increase in packing density of a semiconductor memory, a bit line pitch of the memory array in a semiconductor memory is becoming very high. A parasitic capacitance between neighboring bit lines is becoming larger than a capacitance parasitic on a bit line, which exists between the bit line and the substrate, and a capacitance between the bit line and a line extending above the bit line.
Moreover, since the flash memory generally adopts a method of precharging a bit line in accordance with write data and simultaneously writing all of memory cells connected to one word line (hereinbelow, referred to as one sector), there is a case that 210 bit lines are precharged. In such a case, when all the write data of one sector is xe2x80x9c0xe2x80x9d or only one bit is xe2x80x9c0xe2x80x9d (since when all the write data is xe2x80x9c1xe2x80x9d, the writing operation is not performed), precharging against the parasitic capacitance between neighboring bit lines is not performed. When write data is 1010101 . . . 10, every other bit line is precharged, that is, the charging against all the parasitic capacitance between bit lines is performed. Consequently, the capacitive load on the booster is the heaviest in this case. By the deep examination on a flash memory being developed by the inventors of the present invention, it was found that a variation of about 1 mS at the maximum occurs in the boost time of the internal power source in accordance with the kind of write data.
In the conventional method of determining the write start timing on the basis of time, since the timing has to be determined by using the case of writing the data of xe2x80x9c1010101 . . . 10xe2x80x9d as the worst case regarding the data, the write start timing has to be further delayed. It was clarified that, when the timing is determined in consideration of the worst case with the source voltage of 1.8V, a time allowance of about five times as long as the time necessary to boost the power source voltage to write data of all xe2x80x9c0xe2x80x9d with the source voltage of 3.3V is necessary, so that the write time takes very long.
The inventors then examined the method of monitoring not time but a boosted internal source voltage and, when the internal source voltage reaches a predetermined potential, starting the writing operation. In this case, however, when the internal source voltage does not reach the predetermined potential by the cause such as a leak due to adhesion of a conductive foreign matter on a bit line, it is feared that the program cannot escape from the writing operation. It was also made clear that the method has a drawback that, by providing an internal source voltage monitoring circuit constructed by a resistance dividing circuit and a comparator, an extra resistive load is placed on the booster, and the time required to boost the internal source voltage increases.
An object of the invention is to provide a semiconductor memory having an internal booster such as a flash memory, capable of avoiding a situation that the program cannot escape from the writing operation and promptly finishing the writing operation in accordance with the level of an external source voltage.
The above and other objects and novel features of the present invention will become apparent from the description of the specification and the appended drawings.
The outline of a representative one of inventions disclosed in the specification will be briefly described as follows.
There is provided a semiconductor memory having an internal booster, comprising a voltage detecting circuit such as a limiter for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.
More specifically, there is provided a semiconductor memory having a plurality of memory cells and a booster for generating a boosted voltage on the basis of a source voltage supplied from the outside, for applying the boosted voltage to a selected memory cell when the voltage generated by the booster reaches a predetermined level, comprising: a voltage detecting circuit for detecting whether the boosted voltage has reached a predetermined potential or not; a control circuit capable of controlling start and stop of a boosting operation of the booster; and a timer capable of counting predetermined time. The control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.
According to the means, also in the case where the level of an external source voltage is low and a voltage is not so boosted by the booster, after elapse of predetermined time, data is written to a memory cell. Consequently, the situation that the program cannot be escaped from the writing operation since the boosted voltage does not reach a predetermined potential conventionally occurred can be avoided. When the level of the external source voltage is high and the boosted voltage reaches a predetermined potential in short time, the writing operation is started. Consequently, the writing operation can be promptly finished.
Desirably, switching means for supplying or interrupting the boosted voltage is provided. The switching means receives a control signal from the control circuit and applies the boosted voltage to the selected memory cell. With the configuration, when a plurality of boosted voltages of levels different from each other such as the write voltage and a verify voltage are necessary, without changing the level itself of the voltage generated by the booster, the voltage to be applied to a memory cell can be changed only by operating the switch.
Preferably, a clock generating circuit for generating an internal clock signal is provided. By using the circuit, it becomes unnecessary to generate and supply a clock necessary for the operation of the booster on the outside of the chip of the semiconductor memory, so that the burden on designing of the user is lessened.
The booster operates on the basis of a clock signal for boosting generated by the clock generating circuit, and the timer operates on the basis of a clock signal for counting generated by the clock generating circuit. With the configuration, the clock generating circuit can be commonly used to generate the clock signal for boosting and the clock signal for counting.
The semiconductor memory further has a plurality of word lines. Each of the plurality of memory cells is connected to a corresponding word line, and the boosted voltage is applied to a word line to which the selected memory cell is coupled.
Further, the booster has a positive voltage generating circuit for generating a positive high voltage on the basis of a source voltage from the outside and a negative voltage generating circuit for generating a negative high voltage on the basis of the source voltage from the outside. With the configuration, not only the high voltage necessary for writing but also the high voltage necessary for erasing can be also generated on the inside of the chip.
Each of the plurality of memory cells has a threshold voltage corresponding to data to be stored. Consequently, multi-value information can be stored in a single memory cell.
Data is written/erased to/from each of the plurality of memory cells by using a tunnel phenomenon. In the writing/erasing method using the tunnel phenomenon, as compared with a method of injecting hot electrons into a memory cell by passing a drain current, a higher voltage is generally needed, and a burden is caused by the booster. Consequently, by applying the present invention, the effect is enhanced.
Further, according to another aspect of the invention, there is provided a semiconductor memory having a plurality of memory cells each having a threshold voltage corresponding to data to be stored, a plurality of bit lines, a plurality of data latches provided for the bit lines, and a booster for generating a boosted voltage on the basis of a source voltage supplied from the outside, each of the plurality of memory cells being coupled to a corresponding bit line, the boosted voltage being applied to the memory cell selected when the boosted voltage reaches a predetermined potential, and data being rewritten to the memory cell in accordance with data latched by the data latch, comprising: a voltage detecting circuit for detecting whether the boosted voltage has reached a predetermined potential or not; a control circuit capable of controlling start and stop of a boosting operation of the booster; and a timer capable of counting predetermined time, wherein the control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.
According to the means, since the data latch is provided for each bit line, the writing operation can be performed in a plurality of times. As described above, even when the writing operation is started after elapse of the predetermined time before the boosted voltage reaches the predetermined potential, by increasing the number of writing times, accurate writing can be guaranteed. Thus, the situation that the program cannot be escaped from the writing operation since the boosted voltage does not reach the predetermined potential can be avoided. In the case where the level of the external source voltage is high, when the boosted voltage reaches a predetermined potential, the writing operation is started. Consequently, the writing operation can be promptly finished.
Desirably, each of the memory cells is constructed to store multi-value information by having any one of a plurality of threshold voltages. With the configuration, without enlarging the area of the memory array, the storage capacity can be increased. In this case, a higher boosted voltage is necessary as compared with the case of binary data. By applying the invention, it can be prevented that the program cannot be escaped from the writing operation when the external source voltage is low.
A second voltage boosted by the booster in accordance with data latched by the data latch is applied to the bit line, and the control circuit reserves activation of the timer until the second voltage reaches the predetermined potential. When the writing operation is started before the potential of the bit line becomes sufficiently high, there is the possibility that a xe2x80x9cdisturbxe2x80x9d failure that the threshold voltage of a not-selected memory cell changes occurs. Since the timer is started after the boosted voltage to be applied to the bit line has reached the potential, even when the writing operation is started after elapse of the predetermined time after that, the level of the boosted voltage to be applied to the bit line is guaranteed, so that the occurrence of the disturb failure can be prevented.